Intel Demonstrates Next Generation Process Tech.
Intel Demonstrates Next Generation Process Technology
Intel Corporation has built fully functional SRAM (Static Random Access Memory) chips using 65 nanometer (nm) technology, its next generation high-volume semiconductor manufacturing process. Intel is on track to put this process into production in 2005 using 300 mm wafers.
This new 65 nm (a nanometer is one-billionth of a meter) process combines higher-performance and lower-power transistors, a second-generation version of Intel’s strained silicon, high-speed copper interconnects and a low-k dielectric material. Building chips using the 65 nm process will allow Intel to double the number of transistors it can build on a single chip today.
“This accomplishment puts Intel’s 65 nm technology on a fast track to extend our 15 year record of ramping production on a new process generation every two years. In fact, only 20 months have elapsed since we disclosed achievement of fully functional SRAMs on our 90nm process, which is now ramping,” said Dr. Sunlin Chou, senior vice president and general manager of Intel’s Technology and Manufacturing Group. “The 65 nm process will enable us to make better products at lower cost, as we continue to innovate and extend Moore’s Law.”
Process Technology Details
Advanced transistors: Intel’s new 65 nm process will feature transistors measuring only 35 nm in gate length, which will be the smallest and highest performing CMOS transistors
in high-volume production. By comparison, the most advanced transistors in production today, found in Intel® Pentium® 4 processors, measure 50 nm. Small, fast transistors are the building blocks for very fast processors.
Strained silicon: Intel has integrated a second-generation version of its high-performance strained silicon into this process. Strained silicon provides higher drive current, increasing the speed of the transistors with only a two percent increase in manufacturing cost.
Copper interconnects with new low-k dielectric: The process integrates eight copper interconnect layers and uses a ”low-k” dielectric material that increases the signal speed inside the chip and reduces chip power consumption.
Intel has used its 65 nm process to make fully functional, four megabit SRAM chips with a very small 0.57µm² cell size. Small SRAM cells allow for the integration of larger caches in processors, which increase performance. The SRAM cells have robust operating characteristics, with a solid noise margin indicating very efficient on/off switching properties. Each SRAM memory cell has six transistors: 10 million of these transistors would fit in one square millimeter, roughly the size of the tip of a ball point pen.
“Intel's 65 nm process development is progressing well and we are producing these wafers and chips in our development fab,” said Mark Bohr, Intel Senior Fellow and director of process architecture and integration. “By 2005, we expect to be the first company to have a 65 nm process in manufacturing.”
The 65 nm semiconductor devices were manufactured at Intel’s 300 mm development fab (called D1D) in Hillsboro, Oregon, where the process was developed. D1D is Intel’s newest fab and contains its largest individual cleanroom measuring 176,000 square feet, which is roughly the size of three and a half football fields.
In-House Mask Facility Extends Life of Lithography
Intel’s in-house mask making team has been critical in building advanced masks that extend the existing 193 nm wavelength lithography equipment for use with the 65nm process generation. The company expects to reuse the 193 nm and 248 nm lithography equipment currently used on its 90 nm process, as well as adding some upgraded 193 nm tools. This lowers
implementation costs and ensures a mature tool set for the manufacturing ramp. The 65 nm process is on track to be ramped into high volume in D1D and transferred to other 300 mm manufacturing fabs starting in 2005.
More information can be found in Intel’s Silicon Showcase at http://www.intel.com/research/silicon.
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